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The present disclosure relates to electronic circuits, and in particular, to a low power-dissipation clock gating circuit for driving electronic circuits having differential input/output circuits.
Description of the Related Art
An integrated circuit may include circuits for processing signals. These circuits may receive differential signals that may be shifted in phase. In order to process such differential signals, the integrated circuit may include a clock generating circuit that receives the differential signals and generates a clock signal.
FIG. 1 shows a prior art clock generating circuit that is used to generate a clock signal from the differential input signals. The clock generating circuit in FIG. 1 includes an input differential circuit 10, a first-stage differential-to-single-ended conversion circuit 20, a second-stage differential-to-single-ended conversion circuit 30, and a buffer 40. The input differential circuit 10 receives differential signals VΔ and VΔ* to generate differential signals VΔ/2 and VΔ/2* having half the amplitude of differential signals VΔ and VΔ* and that are shifted by 180° in phase. The differential-to-single-ended conversion circuit 20 converts differential signals VΔ/2 and VΔ/2* to single-ended signals VΔ_a and VΔ_b having substantially the same amplitude as differential signals VΔ and VΔ* and that are shifted by
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